1. Technical Field
The present invention relates to a technology which enhances electric and mechanical reliability of a wiring substrate which has a through electrode formed in a semiconductor chip or the like, a piezoelectric oscillator using the same, and a gyrosensor.
2. Related Art
In recent years, packages in which a resin layer is formed on an active surface of a semiconductor chip called a wafer level chip scale package (WCSP), a rearrangement wiring is formed thereon, and then an external terminal is formed on the wiring have been developed. In such a package, a pad electrode connected to the side of an element such as a piezoelectric oscillator and a pad electrode connected to a mounting destination are formed on the active surface of the semiconductor chip. Further, the pad electrode connected to the mounting destination and the above described wiring are electrically connected by a through electrode which passes through the resin layer, and the pad electrode connected to the element side is electrically connected to a rear surface of the semiconductor chip by the through electrode which passes through the semiconductor chip. Thus, it is possible to provide a configuration in which a front surface of the semiconductor chip is used as a mounting surface having a rearranged external terminal and an element such as a piezoelectric oscillator can be mounted on a rear surface thereof, thereby miniaturizing an overall device. Accordingly, electrical and mechanical reliability of the through electrode formed on the semiconductor chip is obtained.
FIG. 6 illustrates a through electrode in the related art. As shown in FIG. 6, in a wiring substrate 200 on which a semiconductor chip 202, a first insulating layer 204, and a pad electrode 206 which is electrically connected to the semiconductor chip 202 are sequentially stacked, a through electrode 216 in the related art has a configuration in which a first through hole 208 is formed which passes through the semiconductor chip 202 from a side to which the semiconductor chip 202 is exposed toward the pad electrode 206 side and reaches the first insulating layer 204; a second through hole 212 is formed in which a second insulating layer 210 is coated on an inner wall of the first through hole 208 and which has an inner wall smaller in diameter than the inner wall of the first through hole 208 with which the second insulating layer 210 is coated, passes through the second insulating layer 210 and the first insulating layer 204 and reaches the pad electrode 206; the first through hole 208 and the second through hole 212 are filled with a conductive body 214; and the conductive body 214 and the pad electrode 206 are electrically connected. (refer to JP-A-2007-053149).
However, since the through electrode 216 in the related art has a smaller contact area between the pad electrode 206 and the conductive body 214, there is a problem that reliability of electric connection and endurance during heat stress are reduced. Further, when the through electrode 216 in the related art is formed, a process of exposing a pad electrode to a through hole side is required, but at this time, damage occurs in the pad electrode, and thus, there is a concern that reliability of mechanical connection between the pad electrode and the conductive body may be reduced.